1. Field of the Invention
The present invention relates generally to semiconductor memory devices and, more particularly, to a NAND flash memory device.
This application claims priority to Korean Patent Application No. 2005-84731, filed Sep. 12, 2005, the subject matter of which is hereby incorporated by reference in its entirety.
2. Description of Related Art
In order to read data from a memory device, read commands and addresses may be applied sequentially, and according to predetermined timing, to NAND flash memory devices. Once read commands and addresses are inputted, NAND flash memory devices may carry out a sensing operation during a fixed time. Data stored in memory cells of selected rows may be transferred to registers (referred to as a “page buffer circuit”). During the sensing operation, NAND flash memory devices may maintain a ready/busy signal R/nB in a low state. When all data is transferred from memory cells to registers, the ready/busy signal R/nB is transitioned from a low level to a high level. At this time, NAND flash memory devices may transport data stored in registers to data pads in response to a high-to-low transition of read enable signals nRE that may be provided from memory controllers. Memory controllers may take data from the data pads during a low-to-high transition of read enable signals nRE.
The above-mentioned NAND flash memory devices output data, and memory controllers take data, within one cycle of read enable signals nRE. This data output and take mode may be a major obstacle in reducing the cycle time of read enable signal nRE. In general, the operation speed of memory controllers (or hosts) is faster than that of NAND flash memory devices. Therefore the speed at which data may be read from a NAND flash memory device is limited by the speed of the NAND flash memory device. The performance of memory controllers, therefore, depends on that of NAND flash memory devices. Thus, as the performance of NAND flash memory devices is improved, there is a possibility that the performance of memory controllers can be also improved. The performance of NAND flash memory devices may be improved by shortening the time cycle of the read enable signal nRE. However, it may be very difficult to shorten the time cycle of the read enable signal nRE in NAND flash memory devices employing the data output and fetch mode. This will be described in detail hereinafter.
FIG. 1 represents a timing diagram of a conventional flash memory device. In FIG. 1, if ready/busy signal R/nB is transitioned from a low level to a high level, then memory controllers may provide a read enable signal nRE1 to NAND flash memory devices. NAND flash memory devices may also generate an internal clock signal INT_nRE1 that is synchronized with the read enable signal nRE1. The internal clock signal INT_nRE1 may be generated by buffering the read enable signal nRE1. Next, data stored in registers may be synchronized with the internal clock signal INT_nRE1 to be transported by a data transfer path (including a column gate circuit and a data output circuit.) Because the internal clock signal INT_nRE1 is generated by buffering the read enable signal nRE1, a delay time tD1 may exist between the read enable signal nRE1 and the internal clock signal INT_nRE1. Similarly, because data stored in registers is transferred through the data transfer path, it may be loaded on data pads after a delay time tD2 occurring in the data transfer path. That is, the data may be loaded on data pads after the internal clock signal INT_nRE1 is transitioned from a high level to a low level, and a predetermined time tD2 passed.
The read performance of NAND flash memory devices may be improved by reducing the delay times tD1 and tD2. However, the delay times tD1 and tD2 are generally fixed. Therefore, it may be difficult to reduce the delay times tD1 and tD2. One method for improving the read performance of NAND flash memory devices may be to reduce a time cycle of the read enable signal. As stated above, NAND flash memory devices output data, and memory controllers take data within one cycle. However, even if the time cycle of a read enable signal nRE2 is shortened, as shown in FIG. 1, the delay times tD1 and tD2 may not be varied.
The present disclosure is directed in overcoming one or more problems associated with the conventional flash memory device.